1. Field of the Invention
The present invention relates to a semiconductor memory device and methods of operating and manufacturing the same and more specifically to a small size semiconductor device enabling high speed access.
2. Description of the Related Arts
In general, a memory can roughly be sorted to a RAM (Random Access Memory) and a ROM (Read Only Memory). The RAM is further classified into a DRAM (Dynamic RAM) and an SRAM (static RAM). The DRAM stores information depending on charges to be stored in a capacitor. The SRAM stores information in a flip-flop circuit.
The DRAM will be first schematically explained hereunder. In the DRAM developed after the generation of 4K bits, a memory cell having the structure utilizing one N-channel MOS transistor and one capacitor is mainly introduced. Such a memory cell is also employed in the current 1M bits, 4M bits and 16M bits DRAMs.
FIG. 64 is a circuit diagram indicating a memory cell of DRAM. FIG. 65A is a plan view illustrating a structure of a trench type memory cell of DRAM, while FIG. 65B is a cross-sectional view of FIG. 65A along the cutting line B--B. FIG. 64 and FIG. 65 are introduced on pages 158 and 160 of the "Design of CMOS Ultra-LSI", issued on Apr. 25, 1989, Baifukan Publishing Co. Ltd.
As shown in FIG. 64 and FIGS. 65A, 65B, a memory cell DMC for DRAM is composed of one access transistor T1 and one memory capacitor Cs. In the write operation, the potential of word line WL becomes H (logical high) level and access transistors T1 becomes conductive. Thereby, the potential of the bit line BL is transferred to one electrode of the memory capacitor Cs, that is, a memory node M1 via the access transistor T1. When the potential of the bit line BL is H level, the potential of the memory node M1 is also H level and when the potential of the bit line BL is L (logical low) level, the potential of the memory node M1 also becomes L level. Thereby, when the potential of the word line WL becomes L level, the access transistor T1 becomes conductive. As a result, charges are accumulated in the memory capacitor Cs. A constant cell plate potential Vcp is applied to the other electrode of the memory capacitor Cs.
In the read operation, the bit line BL is to the predetermined potential and thereafter the potential of the word line WL becomes H level. Thereby, the access transistor T1 becomes conductive and charges of the memory node M1 are read out to the bit line BL via the access transistor T1. Thereby, the potential of the bit line BL changes from the predetermined potential and a resultant potential difference is amplified by a sense amplifier (not illustrated).
Next, SRAM will be schematically explained. A memory cell for SRAM is structured by a bistable circuit such as a flip-flop circuit. The memory cell for SRAM is roughly classified into several types of cells depending on types of a load element. For example, when an N-channel MOS transistor is used as a load, the cell is called an NMOS load type cell and when a P-channel MOS transistor is used as a load, the cell is called a CMOS type cell. Moreover, when a high resistance is used as a load element, the cell is called a high resistance load type cell. Furthermore, when a P-channel MOS thin film transistor is used as a load element, the cell is called a TFT type cell. In current, the high resistance load type cell is mainly used.
FIG. 66 is a circuit diagram illustrating a memory cell for SRAM. FIG. 67 is a plan view illustrating a structure of memory cell for SRAM. FIG. 66 and FIG. 67 are shown on the page 164 of "Design of CMOS Ultra-LSI".
As shown in FIG. 66 and FIG. 67, a memory cell SMC for SRAM comprises two access transistors T2, T3, high resistances R1, R2 for pulling up the memory nodes M2, M3 up to the power source voltage Vcc and two cross-coupled driver transistors T4, T5.
In the write operation, the potential of the word line WL becomes H level and the access transistors T2, T3 become conductive. Thereby, the potential of the bit line BL is transferred to the memory node M2 via the access transistor T2 and the potential of the bit line /BL is transferred to the memory node M3 via the access transistor T3. For instance, when the bit line BL becomes H level and the bit line /BL becomes L level, the potential of the memory node M2 becomes H level, while the potential of the memory node M3 becomes L level. Subsequently, when the potential of the word line WL becomes L level, the access transistors T2 and T3 become non-conductive. Since high resistances R1, R2 and driver transistors T4, T5 form a bistable circuit (flip-flop), the memory nodes M2, M3 maintain the given potential, respectively.
In the read operation, the potential of the word line WL becomes H level and the access transistors T2 and T3 become conductive. Thereby, the potentials of the memory nodes M2 and M3 are transferred to the bit lines BL and /BL, respectively and these potentials are amplified by the sense amplifiers (not illustrated).
Since the former memory cell for DRAM DMC is formed of one transistor T1 and one capacitor Cs, one memory cell DMC occupies a small area. Therefore, DRAM has a merit of easily realizing a large memory capacity. However, DRAM has also a demerit that it is difficult to operate the sense amplifier at a high speed because charges are read from the capacitor Cs. Therefore, a longer time is required until the corresponding data is outputted from input of an address signal.
FIG. 68 is a timing chart indicating the read operation of DRAM in the page mode. When a row address strobe signal /RAS falls as indicated in FIG. 68(a), the given external address signal Add is fetched as a row address signal X as indicated in FIG. 68(c). Subsequently, as illustrated in FIG. 68(b), when a column address strobe signal/CAS falls, the given external address signal Add is fetched as a column address signal Y1. One memory cell is designated by these row address signal X and column address signal Y1 and the data D1 is read from such memory cell as illustrated in FIG. 68(d). When the column address strobe signal/CAS rises again, the column address signal Y2 is fetched and the data D2 is read from the memory cell designated by the row address signal X and column address signal Y2.
As explained above, here lies a problem that the time Tr (usually, 60 nS) until the data D1 is read first from fall of the row address strobe signal/RAS becomes longer than the time Tc (usually, 15 nS) until the next data D2 is read from fall of the column address strobe signal/CAS.
Moreover, in the DRAM, since charges are stored in the capacitor Cs, amount of charges is reduced with passage of time. Therefore, the DRAM requires the refresh operation by executing the write operation to the capacitor Cs with charges in every predetermined period.
Meanwhile, the latter SRAM has a merit that it does not require the refresh operation because a memory cell SMC thereof is formed of a bistable circuit. Moreover, since the bit lines BL, /BL consisting of a couple of complementary signal lines are used, a sense amplifier can easily be operated at a high speed. However, since SRAM usually uses a memory cell SMC consisting of six elements, it has a demerit that the occupation area of the memory cell SMC becomes larger than the memory cell DMC for DRAM. Therefore, the manufacturing cost of SRAM becomes higher than that of DRAM. Until now, the DRAM having the storage capacity four times that of the SRAM has been realized with the manufacturing technique of the same generation.
By the way, the Japanese Patent Application Laid-open No. 62-222487 discloses a semiconductor memory device wherein data is latched from the DRAM by starting the data read operation from the SRAM circuit and precharging the bit lines of the DRAM circuit and selecting the word lines during such data read operation. Moreover, the Japanese Patent Application Laid-open No. 62-209797 discloses a memory cell of the DRAM circuit is formed of three transistors. In these semiconductor devices, since it is required to provide two row decoders for SRAM and DRAM, current consumption becomes large. Moreover, complicated internal circuits must be provided for controlling the operation timings of SRAM and DRAM and such operation times are also complicated.